Coreinfo

Coreinfo is a utility that displays the mapping between logical processors and the physical processor, NUMA node, and socket they reside on, as well as the caches assigned to each logical processor. It uses low-level Windows APIs (user-mode and kernel-mode) to obtain detailed CPU topology information directly from the operating system. The graphical interface version provides multiple specialized views for examining the system's CPU and cache topology.

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• Core View. Displays all logical processors in a grid layout, illustrating the relationship between logical cores and their physical resources. Each cell represents a logical processor and includes color indicators for Performance-cores (P-Cores) and Efficient-cores (E-Cores). It provides information on the logical processor number, core type, associated cache levels (L1, L2, L3), NUMA node assignment, socket, and group.
• NUMA View. Organizes cores according to their Non-Uniform Memory Access (NUMA) node assignments. It groups cores by node, showing the count of physical and logical cores per node and the available memory on each. It facilitates understanding of memory locality and access patterns by displaying the distribution of cores and the count of efficient cores per node.
• Socket View. Presents cores organized by their physical CPU socket. Useful for analyzing multi-socket systems and resource distribution at the socket level. It shows the number of physical sockets, cores per socket (physical and logical), socket-level cache information, and the NUMA nodes associated with each socket.
• CPU Features View. Displays a comprehensive list of the processor's capabilities, instruction set extensions, and hardware features supported by the CPU. It includes a search bar to locate specific features and visual status indicators (supported/unsupported) using color coding. Categories include virtualization, 64-bit support, instruction sets (SSE, AVX, AES), power management, and security features.
• NUMA Performance View. Provides a matrix visualization of memory access costs between different NUMA nodes. The NxN grid (where N is the number of nodes) shows the relative access costs from a source node (row) to a target node (column), helping to identify performance bottlenecks in NUMA systems.
• Core Distance View. Exhibits a detailed heat map of communication costs between individual CPU cores. The NxN matrix (N = number of logical processors) uses color coding (green/blue for low latency, yellow/orange for medium latency, red for high latency) to represent the relative distance or latency between cores, offering insights into core-to-core communication efficiency.
• Core Selection and Detail. Clicking on a core in the Core, NUMA, or Socket views displays detailed information in the bottom panel. This information includes the logical processor number, mask and affinity, the complete cache hierarchy (L1 data, L1 instruction, L2, and L3 caches with their size, associativity, and line size), and topology assignments (NUMA node, socket, group).
• Cache Map Toggle. In the Core View, this feature allows switching between the default view mode (logical layout of cores) and the cache map mode, which rearranges the display to illustrate shared cache relationships between cores.
• Features View Search. The CPU Features View incorporates a search functionality that filters the list of features in real-time as the user types the feature name or abbreviation, making it easy to locate support for specific technologies like VMX, AVX-512, or SGX.
• Save To File. The interface includes an option to dump all CPU topology data to a file. The output format is identical to that of the command-line version, allowing for analysis or documentation of the system configuration.

Coreinfo was created by Mark Russinovich, a renowned software engineer and co-founder of Sysinternals, a company dedicated to creating advanced utilities for Windows systems that was acquired by Microsoft in 2006. The first version of Coreinfo dates back to 2008, initially developed as a command-line tool to delve deeper into understanding processor topology on Windows systems. The program is primarily written in C and C++, leveraging native system APIs to obtain low-level information.