Memtest86+

Memtest86+ is a standalone memory testing program for x86 and x64 computers. It operates independently of any operating system. The software writes complex data patterns to RAM, reads them back, and compares results to detect faulty memory cells, bit errors, addressing problems, and unwanted interactions between memory modules.

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• Basic addressing test. Verifies that each memory address can be accessed uniquely and correctly. Writes a unique pattern to every memory location, then reads those values to confirm no address overlaps, decoder faults, or issues with the memory controller's address decoding logic.
• Walking Ones and Walking Zeros test. Shifts a single '1' bit (or '0' bit) through all bit positions within a memory register. This detects coupling faults between adjacent cells where changing one bit's state corrupts the state of a physically neighboring bit inside the same DRAM chip.
• Random number sequence test. Generates pseudo-random number sequences, writes them to memory, then reads back and compares against the original pattern. Effective at discovering intermittent errors that depend on the specific data values stored in memory cells.
• Block move test. Copies large blocks of data from one memory region to another, then verifies data integrity in both source and destination locations. Detects errors in the data bus and in the fast block transfer mechanism used by certain processor instructions.
• Thermal stability test. Subjects memory to continuous write-read cycles using patterns that generate maximum cell activity. Heat produced during operation can reveal errors that only appear when DRAM chips reach elevated temperatures, not detectable in cold tests.
• Row Hammer test. Repeatedly activates adjacent rows of memory cells to induce charge leakage in non-selected rows. Determines whether memory is vulnerable to the Row Hammer phenomenon where excessive activation of one row corrupts data in neighboring rows.
• Processor cache test. Writes and verifies patterns while deliberately controlling L1 and L2 cache usage. By forcing accesses that either use or bypass the cache, identifies errors originating not in RAM but in the CPU's own cache memory, isolating the root cause.
• Per-module addressing test. Organizes tests by individual memory banks and chips when the system architecture permits. This function pinpoints which physical module (DIMM or soldered) contains the error, enabling selective replacement without changing all memory.
• Checkerboard pattern test. Writes an alternating '1' and '0' pattern like a chessboard, then inverts and rewrites the pattern. Detects short-circuit failures between adjacent bit lines or between cells sharing the same word line, a common defect in high-density memory.
• Error logging and BadRAM mapping test. Records the exact address of each detected error and allows marking those regions as defective. On compatible systems, Memtest86+ can pass this bad address list to the operating system's boot loader so that the OS avoids using those memory zones.
• Symmetric multiprocessing (SMP) test. On multi-core or multi-processor systems, executes simultaneous tests on different cores to verify shared memory coherence. Detects synchronization errors between cores and problems in the MESI protocol (Modified, Exclusive, Shared, Invalid) of the cache coherency system.
• Increment-decrement pattern test. Writes values that progressively increase or decrease across memory addresses. This sequence is sensitive to distance-dependent data coupling errors, a type of failure that other linear tests do not always detect.

Memtest86+ was created in 2004 by Samuel Demeulemeester as a fork of the original Memtest86 by Chris Brady. The program is written in x86 assembly language and C, with low-level components for direct booting from BIOS or UEFI. Development continued until 2013 and was reactivated in 2020 by a contributor team led by Martin Whitaker, who unified support for modern hardware, DDR4 and DDR5 memory, and 64-bit UEFI booting.

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